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may 200 2 2002 fairchild semiconductor corporation FDC654P rev e (w) FDC654P single p - channel logic level powertrench mosfet general description this p - channel logic level mosfet is produced using fairchild?s advanced powertrench process. it has been optimized for battery power management applications. applications batt ery management load switch battery protection features ? 3.6 a, ? 30 v. r ds(on) = 75 m w @ v gs = ? 10 v r ds(on) = 125 m w @ v gs = ? 4.5 v low gate charge (6.2 nc typical) high performance trench technology for extremely low r ds(on) d d d s d g supersot -6 tm 6 5 4 1 2 3 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain - source voltage ? 30 v v gss gate - source voltage 2 0 v i d drain current ? continuous (note 1a) ? 3.6 a ? pulsed ? 10 maximum power dissipation (note 1a) 1.6 w p d (note 1b) 0.8 t j , t stg operating and storage junction temperature range ? 55 to +150 c thermal characteristics r q ja thermal resistance, junction - to - ambient (note 1a) 78 c/w r q jc thermal resistance, junction - to - case (note 1) 30 c/w package marking and ordering information device marking device reel size tape width quantity .654 FDC654P 7?? 8mm 3000 units FDC654P
FDC654P rev e (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain ? source breakdown voltage v gs = 0 v, i d = ? 250 m a ? 30 v d bv dss d t j breakdown voltage temperature coeff icient i d = ? 250 m a,referenced to 25 c ? 22 mv/ c i dss zero gate voltage drain current v ds = ? 24 v, v gs = 0 v ? 1 m a i gssf gate ? body leakage, forward v gs = 2 0 v, v ds = 0 v 100 na i gssr gate ? body leakage, reverse v gs = ? 2 0 v , v ds = 0 v ? 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = ? 250 m a ? 1 ? 1.9 ? 3 v d v gs(th) d t j gate threshold voltage temperature coefficient i d = ? 250 m a, referenced to 25 c 4 mv/ c r ds(on) static drain ? source on ? resistance v gs = ? 10 v, i d = ? 3.6 a v gs = ? 4.5 v, i d = ? 2.7 a v gs = ? 10 v, i d = ? 3.6a,t j =125 c 63 100 90 75 125 115 m w i d(on) on ? state drain current v gs = ? 4.5 v, v ds = ? 5 v ? 5 a g fs forward transconductance v ds = ? 5 v, i d = ? 3.6 a 6 s dynamic characteristics c iss input capacitance 298 pf c oss output capacitance 83 pf c rss reverse transfer capacitance v ds = ? 15 v, v gs = 0 v, f = 1.0 mhz 39 pf switching characteristics (note 2) t d(on) turn ? on delay time 6 12 ns t r turn ? on rise time 13 23 ns t d(off) turn ? off delay time 11 20 ns t f turn ? off fall time v dd = ? 15 v, i d = ? 1 a, v gs = ? 10 v, r gen = 6 w 6 12 ns q g total gate charge 6.2 9 nc q gs gate ? source charge 1 nc q gd gate ? drain charge v ds = ? 15 v, i d = ? 3.6 a, v gs = ? 10 v 1.2 nc drain ? source diode characteristics and maximum ratings i s maximum continuous drain ? source diode forward current ? 1.3 a v sd drain ? source diode forward voltage v gs = 0 v, i s = ? 1.3 a (note 2) ? 0.8 ? 1.2 v notes: 1. r q ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. a) 78c/w when mounted on a 1in 2 pa d of 2 oz copper b) 156c/w when mounted on a minimum pad of 2 oz copper scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 m s, duty cycle < 2.0% FDC654P
FDC654P rev e (w) typical characteristics 0 3 6 9 12 15 0 1 2 3 4 5 -v ds , drain to source voltage (v) -i d , drain current (a) v gs = -10v -3.5v -3.0v -4.5v -4.0v -5.0v -6.0v 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 3 6 9 12 15 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -3.5v -6.0v -5.0v -4.0v -10v -4.5v -7.0v figure 1. on - region characteristics. figure 2. on - resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = -3.6a v gs = -10v 0.05 0.1 0.15 0.2 0.25 0.3 2 4 6 8 10 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -1.8a t a = 125 o c t a = 25 o c figure 3. on - resistance variation with temperature. figure 4. on - resistance variation with gate - to - sourc e voltage. 0 2 4 6 8 10 1 2 3 4 5 -v gs , gate to source voltage (v) -i d , drain current (a) t a = -55 o c 25 o c 125 o c v ds = -5.0v 0.0001 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) v gs = 0v t a = 125 o c 25 o c -55 o c figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. FDC654P
FDC654P rev e (w) typical characteristics 0 2 4 6 8 10 0 1.4 2.8 4.2 5.6 7 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -3.6a v ds = -5v -10v -15v 0 100 200 300 400 0 6 12 18 24 30 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage (v) -i d , drain current (a) dc 1s 100ms 100 m s r ds(on) limit v gs = -10v single pulse r q ja = 156 o c/w t a = 25 o c 10ms 1ms 10 m s 0 2 4 6 8 10 0.01 0.1 1 10 100 t 1 , time (sec) p(pk), peak transient power (w) single pulse r q ja = 156c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r q ja (t) = r(t) + r q ja r q ja = 156 o c/w t j - t a = p * r q ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1b. transient thermal response will change depending on the circuit board design. FDC654P

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